Intel x86-64 ISA Manual Summary

1. Introduction

The Intel x86-64 Instruction Set Architecture (ISA) is defined across multiple detailed volumes in Intel's architecture documentation. This appendix distills the most relevant technical highlights, updated after 2020, into a concise summary tailored for assembler developers. It includes structural overviews of the instruction format, register set, addressing modes, encoding styles, and control mechanisms essential for building a compliant and future-ready x86-64 assembler.

2. Architecture Overview

The x86-64 architecture, also known as Intel 64 or AMD64, extends the legacy IA-32 instruction set to support 64-bit general-purpose registers and addressing. Key features include:

• 64-bit Linear Address Space

• 8 Additional General-Purpose Registers (R8–R15)

• 64-bit Instruction Pointer (RIP)

• REX Prefix for Operand Size and Register Extension

• Mandatory Use of SSE/AVX for Floating-Point and SIMD

• Support for Multiple Operating Modes: Real, Protected, Compatibility, and 64-bit Long Mode

3. Instruction Format

Each x86-64 instruction is composed of several byte-level fields:

1. Prefixes (optional, up to 4 legacy + 1 REX/EVEX)

2. Opcode Bytes (1 to 3 bytes)

3. ModR/M Byte (encodes register/memory operations)

4. SIB Byte (optional for scaled indexed addressing)

5. Displacement (optional)

6. Immediate (optional)

Advanced encodings like VEX and EVEX introduce additional complexity and support for wider SIMD registers.

4. Prefixes

Prefix bytes modify the instruction behavior:

• Legacy Prefixes:

  • Lock (F0)

  • Segment override (2E, 36, 3E, etc.)

  • Operand-size override (66)

  • Address-size override (67)

• REX Prefix (64-bit mode only):

  • Extends registers and enables 64-bit operand size

  • Format: 0100WRXB

    • W: 64-bit operand

    • R/X/B: Extend reg, index, and base fields

• VEX Prefix: Used for AVX instructions, replaces some legacy prefixes

• EVEX Prefix: Used in AVX-512 instructions

5. Register Set

General-Purpose Registers (64-bit):

• RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP

• R8–R15: Added in x86-64

Each can be accessed in 64-, 32-, 16-, or 8-bit forms.

SIMD and Floating Point:

• XMM0–XMM31: 128-bit

• YMM0–YMM31: 256-bit (AVX)

• ZMM0–ZMM31: 512-bit (AVX-512)

Segment Registers:

• CS, DS, SS, ES, FS, GS

Control Registers:

• CR0, CR2, CR3, CR4, CR8

6. Addressing Modes

Addressing in x86-64 uses combinations of:

• Base Register + Index Register × Scale + Displacement

Formally: [base + index * scale + displacement]

Scale factors: 1, 2, 4, or 8 SIB (Scale-Index-Base) byte is used to encode this mode.

Memory operand sizes can be 8, 16, 32, 64, 128, or more, depending on the instruction.

7. Instruction Groups

Instructions are categorized by function:

• Data Transfer: MOV, XCHG, PUSH, POP

• Arithmetic/Logic: ADD, SUB, IMUL, AND, XOR

• Control Flow: JMP, CALL, RET, Jcc, LOOP

• String Operations: MOVS, CMPS, SCAS

• Bit/Byte Manipulation: BT, BSF, BSR, SHL, ROL

• Floating Point: FLD, FSTP, FADD, FSUB

• SIMD Instructions: MOVDQA, ADDPS, VPADDQ, VADDPS

• System Instructions: HLT, CLI, STI, SYSENTER, SYSCALL

8. Control Flags

Flags affected by instructions and tested by control flow include:

• CF (Carry)

• PF (Parity)

• AF (Auxiliary Carry)

• ZF (Zero)

• SF (Sign)

• OF (Overflow)

These flags reside in the RFLAGS register and are tested by conditional jump (Jcc) instructions.

9. Modes of Operation

• Real Mode: 16-bit compatibility, direct access to hardware

• Protected Mode: 32-bit linear memory, paging, privilege levels

• Compatibility Mode: 32-bit programs on 64-bit OS

• Long Mode: Full 64-bit addressing and extended registers

Long Mode is the primary target for modern x86-64 assemblers.

10. Modern Extensions (Post-2020)

Recent additions to the ISA include:

• AVX-512: 512-bit vector operations, with new predicate masking

• AMX (Intel Advanced Matrix Extensions): Targeting AI and matrix workloads

• TSX (Transactional Synchronization Extensions): Lock elision

• Control-Flow Enforcement (CET): Shadow stacks and indirect branch tracking

• Key Locker: Hardware crypto enhancements

• Serialized Instructions (SERIALIZE, ENQCMD): Ensure ordering and hardware queue interactions

Assembler authors should account for feature detection via CPUID and properly encode new instruction formats like EVEX.

11. Summary

This appendix has outlined the essential architecture and encoding rules of the x86-64 ISA from an assembler developer’s perspective. Understanding the register architecture, instruction format, and operand encodings provides the groundwork necessary to implement correct, optimized, and modern assembler support. Future-proofing your assembler will involve tracking ongoing ISA extensions while retaining robust support for core architectural concepts.